Mechanism for efficient implementation of software pipelined loops in VLIW processors
US8447961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2010 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jan 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.