Method and system for parallel processing of IC design layouts
US8448096B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Sep 28, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.