Semiconductor module
US8450793B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2010 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Dec 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/142
Abstract
A controlled-punch-through semiconductor device with a four-layer structure is disclosed which includes layers of different conductivity types, a collector on a collector side, and an emitter on an emitter side which lies opposite the collector side. The semiconductor device can be produced by a method performed in the following order: producing layers on the emitter side of wafer of a first conductivity type; thinning the wafer on a second side; applying particles of the first conductivity type to the wafer on the collector side for forming a first buffer layer having a first peak doping concentration in a first depth, which is higher than doping of the wafer; applying particles of a second conductivity type to the wafer on the second side for forming a collector layer on the collector side; and forming a collector metallization on the second side. At any stage particles of the first conductivity type can be applied to the wafer on the second side for forming a second buffer layer with a second peak doping concentration lower than the first peak doping concentration of the first buffer layer, but higher than the doping of the wafer. A third buffer layer can be arranged between the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.