Semiconductor structure with a planar Schottky contact
US8450798B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 21, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Oct 21, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
Abstract
A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the top surface of the semiconductor layer adjacent the trench so as to form a Schottky contact with the top surface of the semiconductor layer adjacent the trench. A surface of the semiconductor layer in the Schottky region is lower relative to a surface of the semiconductor layer in the FET region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.