Dual mode sigma delta analog to digital converter and circuit using the same
US8451051B2 · kind B2 · utility
3Cited by
8References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 4, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Dec 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/30
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention provides a dual mode sigma delta analog to digital converter (ADC), which only in one hardware implementation, used for low IF and near zero IF receiver. The dual mode sigma delta ADC comprises a first switched-capacitor integrator; a second switched-capacitor integrator; a quantizer; a feedback circuit and a mode device. By switching the mode device on or off, one could easily change the configuration of the disclosed ADC to decide the receiving signal falling in low-IF or near zero IF.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.