Pipelined ADC inter-stage error calibration
US8451152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jul 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.