Pipelined ADC calibration
US8451154B2 · kind B2 · utility
3Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2009 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Feb 14, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of calibrating a pipelined analog to digital converter having a plurality of DAC elements and an additional calibration DAC element is provided. In the method as provided herein, a combination of positive, negative and zero reference voltages are applied to the element under calibration and positive and negative reference voltages are applied to the additional calibration DAC element to obtain four calibration states. An error of the DAC element under calibration is extracted by calculating an average of the difference between the four calibration states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.