Low power high speed pipeline ADC
US8451160B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jul 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved. A multiplying analog to digital converter (MDAC) circuit receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate a residue output voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.