System for reducing power consumption and increasing speed of content-addressable memory
US8451640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jun 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.