Multi-level memory devices and methods of operating the same
US8451656B2 · kind B2 · utility
1Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.