Dual-port SRAM with bit line clamping
US8451679B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Feb 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory is provided that includes: a write driver for selectively driving a driven pair of bit lines selected from a plurality of bit line pairs during a write operation; a first stage clamping circuit operable to clamp a pair of internal nodes to a clamping voltage, wherein the first stage clamping circuit is further operable to unclamp the pair of internal nodes during the write operation; a bit line multiplexer for selectively coupling the driven bit line pair to the pair of internal nodes; and a second stage clamping circuit operable to clamp the plurality of bit line pairs to the clamping voltage, wherein the second stage clamping circuit is further operable to unclamp the driven bit line pair during the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.