On-chip full eye viewer architecture
US8451883B1 · kind B1 · utility
13Cited by
5References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2009 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jun 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/048
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with an equalized serial input signal. The device may include an equalizer and eye viewer circuitry. The equalizer may receive and perform equalization on a serial input signal to produce the equalized serial input signal, and the eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the equalized serial input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.