Automated conversion of synchronous to asynchronous circuit design representations
US8453079B2 · kind B2 · utility
9Cited by
17References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 31, 2009 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jun 17, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.