Semiconductor device and method for manufacturing the same
US8455925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Feb 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M>N), capacitance elements are provided over the interconnect layers comprised of (M−N) layers or (M−N+1) layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.