Electrically isolated power semiconductor package with optimized layout

US8455987B1 · kind B1 · utility

Assignee

• IXYS, LLC · US

Inventors

• Thomas Spann · Ergolding, DE
• Holger Ostmann · Rodgau, DE
• Kang Rim Choi · Cupertino, US

Key dates

• Filing date: Apr 30, 2010
• Grant date: Jun 4, 2013
• Expiry date: Sep 21, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.