Phase-locked loop lock detect
US8456206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Jun 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.