State retention circuit and method of operation of such a circuit
US8456214B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Feb 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal. As a result, the isolation structure isolates the storage element from the input during the retention mode of operation, causing the storage element to retain its stored state prior to entry of the retention mode of operation irrespective of changes in the clock signal or changes in the input during the retention mode of operation. Such a design provides a clock independent pul…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.