Patent · US Active

Failsafe oscillator monitor and alarm

US8456243B2 · kind B2 · utility

9Cited by
4References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 26, 2010
Grant dateJun 4, 2013
Priority date
Expiry dateFeb 22, 2032

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R19/16585
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A failsafe oscillator monitor and alarm circuit receives clock pulses from an external oscillator that if a failure thereto occurs, the failsafe oscillator monitor and alarm circuit will notify a digital processor of the external oscillator failure. The failsafe oscillator monitor and alarm circuit is a very low current usage circuit that charges a storage capacitor with clock pulses from the external oscillator when functioning normally and discharges the storage capacitor with a constant current sink if the external oscillator stops functioning. When the voltage charge on the storage capacitor becomes less than a reference voltage an alarm signal is sent to the digital processor for exception or error handling of the failed external oscillator.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.