DRAM device with built-in self-test circuitry
US8456934B2 · kind B2 · utility
8Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2012 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Mar 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.