Process for testing the resistance of an integrated circuit to a side channel analysis
US8457919B2 · kind B2 · utility
5Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Aug 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/302
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.