Performing a local reduction operation on a parallel computer
US8458244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2012 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Aug 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17318
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel computer including compute nodes, each including two reduction processing cores, a network write processing core, and a network read processing core, each processing core assigned an input buffer. Copying, in interleaved chunks by the reduction processing cores, contents of the reduction processing cores' input buffers to an interleaved buffer in shared memory; copying, by one of the reduction processing cores, contents of the network write processing core's input buffer to shared memory; copying, by another of the reduction processing cores, contents of the network read processing core's input buffer to shared memory; and locally reducing in parallel by the reduction processing cores: the contents of the reduction processing core's input buffer; every other interleaved chunk of the interleaved buffer; the copied contents of the network write processing core's input buffer; and the copied contents of the network read processing core's input buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.