Memory controller idle mode
US8458429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2007 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Sep 25, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.