Device and memory system for memory management using access frequency information
US8458436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2012 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Jan 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.