Patent · US Active

High speed syndrome-based FEC encoder and system using same

US8458575B2 · kind B2 · utility

4Cited by
33References
6Claims
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Key dates

Filing dateFeb 13, 2009
Grant dateJun 4, 2013
Priority date
Expiry dateApr 6, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03M13/1515
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.