Patent · US Active

Bios routine avoidance

US8458726B2 · kind B2 · utility

2Cited by

2References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Vincent J. Zimmer · Federal Way, US
Jiewen Yao · Shanghai, CN

Key dates

Filing date	Dec 3, 2007
Grant date	Jun 4, 2013
Priority date	—
Expiry date	Sep 18, 2030

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02B30/70
WIPO fieldThermal processes and apparatus
WIPO sectorMechanical engineering

Abstract

A method, computer readable medium, and device are disclosed. In one embodiment the method includes determining whether an entry exists in a firmware interface table to direct the processor to handle the event in a non-legacy mode. This is done after an event for a processor that triggers a legacy mode processor handling routine. The method also includes the processor handling the event in the non-legacy mode when the entry exists.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.