Hardware-implemented hypervisor for root-of-trust monitoring and control of computer system
US8458791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Jul 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for modifying a processor system with hypervisor hardware to provide protection against malware. The processor system is assumed to be of a type having at least a CPU and a high-speed bus for providing data links between the CPU, other bus masters, and peripherals (including a debug interface unit). The hypervisor hardware elements are (1) a co-processor programmed to perform one or more security tasks; (2) a communications interface between the co-processor and the debug interface unit; (3) a behavioral interface on the high-speed bus, configured to monitor control signals from the CPU, and (4) an access controller on the high-speed bus, configured to store access control data, to intercept requests on the high-speed bus, to evaluate the requests against the access control data, and to grant or deny the requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.