Semiconductor device capable of suppressing generation of cracks in semiconductor chip during manufacturing process
US8461690B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2010 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a chip stacked body where a plurality of semiconductor chips are stacked, and penetration electrodes respectively formed in the semiconductor chips are electrically interconnected in stacking order of the semiconductor chips, a first support member that is disposed to face a first semiconductor chip formed in one end of the chip stacked body, and including electrodes electrically connected to the penetration electrodes of the first semiconductor chip, and a wiring board that is disposed to face a second semiconductor chip formed in an end opposed to the one end of the chip stacked body, and including external electrodes on a surface opposed to a surface facing the second semiconductor chip that is to be electrically connected to the penetration electrodes of the second semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.