Device for storing pulse latch with logic circuit
US8461866B2 · kind B2 · utility
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1Claims
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Key dates
| Filing date | Apr 20, 2011 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Apr 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0375
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for storing pulse latch with logic circuit and thus having signal maintaining function is provided, wherein the device is composed of a data signal, a scan data input signal, a stored signal, a choosing data input signal, a time clock signal, a restoring signal, a first signal channel, a scan latch, a second signal channel, a pulse latch, a normal output signal, an output signal, a first OR gate, a second OR gate, a third OR gate, a AND gate and an inverter connecting to one another. The device may store the data when being switch off and restore the data when being switch on again.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.