Low latency inter-die trigger serial interface for ADC
US8461879B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 2012 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | May 28, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1225
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A packaged controller for closed-loop control applications includes two dice packaged together in a semiconductor package. The first die is optimized for digital circuitry and includes a processor, an ADC, a serial bus interface, and a sequencer. The second die is optimized for analog circuitry and includes a serial bus interface, a plurality of sample/hold circuits, and an analog multiplexer. The sequencer on the first die causes a series of multi-bit values to be communicated serially across a low latency serial bus to the second die, and thereby controls the analog multiplexer and the asserting of a sample/hold signal on the second die. Under control of the sequencer, multiple voltages are captured simultaneously on the second die, and then are multiplexed one by one to the ADC on the first die for conversion into digital values. The architecture reduces complexity and cost of the overall packaged controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.