Patent · US Active

Hybrid digital-analog phase locked loops

US8461885B2 · kind B2 · utility

10Cited by

0References

28Claims

0Family size

Assignee

Analog Devices, Inc. · US

Inventors

Khiem Quang Nguyen · Tewksbury, US
Jie Fu · Beijing, CN
Xiaoting Zhu · Shanghai, CN

Key dates

Filing date	Jun 8, 2011
Grant date	Jun 11, 2013
Priority date	—
Expiry date	Dec 13, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/23
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A digital PLL may be combined with an analog PLL so that the output of the digital PLL is at a frequency high enough to maintain stability in the analog PLL when an initial reference clock signal is too low to maintain stability in the analog PLL. The digital PLL may include a scaling circuit, such as a frequency divider in the feedback path of the PLL, to generate the higher frequency output signal from the lower frequency reference input signal. The digital PLL may also use an on-chip free run ring oscillator as the clock for the digital PLL engine.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.