Apparatus and method for well buffering
US8461897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2010 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Dec 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for well buffering are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well, and the gate is formed adjacent the well between the source and drain. The source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a gate bias control block for biasing the gate voltage of the switch, a well bias control block for biasing the well voltage of the switch, and a buffer circuit for increasing the impedance between the well bias control block and the well of the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.