Radio frequency (RF) receiver with dynamic frequency planning and method therefor
US8463223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2012 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Jun 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2215/065
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A radio frequency (RF) receiver comprises an analog receiver, a digital processor, a clock synthesizer, and a microcontroller. The analog receiver has an input for receiving an RF input signal, and an output for providing a digital intermediate frequency (IF) signal. The digital signal processor has a first input for receiving the digital IF signal, a second input for receiving a clock signal, and a signal output for providing an IF output signal. The clock synthesizer has an input for receiving a clock control signal, and an output for providing the clock signal. The a microcontroller has an input for receiving a channel selection signal, wherein the microcontroller provides the clock control signal to control a frequency of the clock signal dynamically in response to a channel selection input to reduce interference of sub-harmonics created by the clock signal on the analog receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.