Digital signal processing block architecture for programmable logic device
US8463832B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2008 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Apr 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.