Mechanism for a shared serial peripheral interface
US8463968B2 · kind B2 · utility
0Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2005 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Oct 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a computer system is disclosed. The computer system includes a flash memory device, a serial peripheral interface (SPI) coupled to the flash memory device, a network controller coupled to the SPI; and a chipset coupled to the SPI. The chipset includes an arbiter to arbitrate between the network controller and the chipset for control of the SPI to access the flash memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.