Extended message signal interrupt
US8463969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Jul 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.