Programmable filter processor select algorithm and parameters and pass time/angle stamp in parallel with A/D data in pipelined logic
US8464027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2008 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Feb 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filter algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit being developed to generate control commands for the second memory and the logic unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.