Semiconductor integrated circuit chip and layout method for the same
US8466497B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2011 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Oct 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit chip mounted on a substrate by flip chip bonding includes: a plurality of electrode pads; a corner portion of a flat periphery of an inner layer; a first linear region adjoining one side of the corner portion; a second linear region adjoining another side of the corner portion; and a third linear region adjoining a side of the first linear region opposite to the side adjoining the corner portion. A circuit core placeable region is provided in at least part of the corner portion and the first linear region. A plurality of IO cells connected to the electrode pads are arranged in the second and third linear regions. The IO cells in the second linear region are connected to the electrode pads arranged inwardly in n rows×n columns from a corner of the chip above the corner portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.