Semiconductor device and manufacturing method therefor
US8466540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2010 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Apr 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.