Method and apparatus for testing a memory device
US8466707B2 · kind B2 · utility
7Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2010 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Sep 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.