Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics
US8467342B2 · kind B2 · utility
8Cited by
40References
9Claims
0Family size
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Key dates
| Filing date | Jan 6, 2011 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Sep 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/254
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.