Secure processor
US8468364B2 · kind B2 · utility
25Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 10, 2006 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Apr 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A secure hardware comprises a secure pipe, a secure DMA, a secure assist and a secure bus, which connects between those blocks. The secure pipe stores a common encryption key in an encryption key table so as not to be able to access from software. The secure DMA comprises a data common key system process function and a hashing process function. The secure assist comprises a common key system process function and an authentication process function, receives an issued command from a program executed by the processor core via a public IF, and performs setting/control of the secure pipe and the secure DMA via the secure bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.