Integrated device, layout method thereof, and program
US8468376B2 · kind B2 · utility
0Cited by
20References
17Claims
0Family size
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Key dates
| Filing date | Feb 16, 2012 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Feb 16, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated device includes at least one data processing device and at least one memory macro accessible by the data processing device. The data processing device and the memory macro are laid out so that a memory address and a power consumption have a correlation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.