Method and apparatus for designing a system on multiple field programmable gate array device types
US8468476B1 · kind B1 · utility
3Cited by
16References
21Claims
0Family size
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Key dates
| Filing date | Mar 21, 2011 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Mar 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system to be implemented on a target device includes generating a register transfer language (RTL) representation of the system from a description of the system without pipelined delays. The RTL representation of the system includes pipelined delays to facilitate timing of the system as implemented on a target device identified by a designer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.