Method for reducing interfacial layer thickness for high-k and metal gate stack
US8470659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2012 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Aug 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.