Method of manufacturing a 3-D vertical memory
US8470671B1 · kind B1 · utility
12Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Oct 24, 2012 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Oct 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
Abstract
A novel method for manufacturing a 3-D vertical memory comprising the steps of dividing a multilayer structure composed of insulating intermediate layers and sacrificial intermediate layers into a first multilayer structure and a second multilayer structure, replacing the sacrificial intermediate layers in the multilayer structures with metal intermediate layers, and manufacturing the channel structure in two multilayer structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.