Substrate with embedded patterned capacitance
US8470680B2 · kind B2 · utility
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12References
21Claims
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Key dates
| Filing date | Jul 28, 2008 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Aug 24, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/435
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.