Layout and pad floor plan of power transistor for good performance of SPU and STOG
US8471299B2 · kind B2 · utility
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29References
17Claims
0Family size
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Key dates
| Filing date | Aug 23, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Dec 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.