Battery fault tolerant architecture for cell failure modes parallel bypass circuit
US8471529B2 · kind B2 · utility
10Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Sep 26, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T10/70
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A by-pass circuit for a battery system that disconnects parallel connected cells or modules from a battery circuit or controls the current through the parallel connected cells or modules. If a cell has failed or is potentially failing in the system, then the by-pass circuit can disconnect the cell or module from other cells or modules electrically coupled in parallel. If a cell or module has a lower capability than another cell or module, then the by-pass circuit can control the current to the cell or module to maximize the performance of the system and prevent the system from creating a walk-home condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.