High-speed frequency divider architecture
US8471607B1 · kind B1 · utility
7Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Dec 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed clock frequency divider circuit is provided that uses a first shift register loop-back circuit and a second shift-register loop-back circuit to shift a predetermined array of bits therethrough. The first shift register loop-back circuit is clocked on a rising clock edge of an input clock signal, while the second shift register loop-back signal is clocked on a negative edge of the input clock signal. The outputs of the first and second loop-back shift registers are ORed to provide a 50% duty cycle output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.