Two-stage analog-to-digital converter using SAR and TDC
US8471751B2 · kind B2 · utility
37Cited by
11References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.